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Interconnect-aware Low Power High-level Synthesis

Lin Zhong and Niraj K. Jha
Department of Electrical Engineering
Princeton University
Princeton, NJ 08544
{lzhong, jha}@ee.princeton.edu [*] [*]

Abstract:

Interconnects (wires, buffers, clock distribution networks, multiplexers and busses) consume a significant fraction of total circuit power. In this work, we demonstrate the importance of optimizing on-chip interconnects for power during high-level synthesis. We present a methodology to integrate interconnect power optimization into high-level synthesis. It not only reduces datapath unit power consumption in the resultant register-transfer level (RTL) architecture, but also optimizes interconnects for power. Physical design information and coupling capacitance is taken into account to estimate interconnect power consumption accurately for deep sub-micron (DSM) technologies. We show that there is significant spurious ($i.e.$, unnecessary) switching activity in the interconnects and propose techniques to reduce it. Compared with interconnect-unaware power-optimized circuits, interconnect power can be reduced by 53.1% on an average, while overall power is reduced by an average of 26.8% with negligible area overhead. Compared with area-optimized circuits, the interconnect power reduction is 72.9% and overall power reduction is 56.0% with 44.4% area overhead.




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Next: Introduction
Lin Zhong 2003-10-11